In many VLSI integrated circuit devices there is a need to fabricate transistors that have different electrical performance characteristics. For example, static-random-access-memory (SRAM) cells suffer stability problems as the cell size is reduced. To function properly, the SRAM memory cell, when charged, must hold a voltage level, either high (logic 1) or low (logic 0). When reading data from the cell, the cell current generated as the pass transistor turns on must not flip the voltage level at the internal cell nodes. To stabilize the cell, the driver transistor is fabricated to have a higher current gain than the pass transistor. Usually, the current gain relationship is controlled by adjusting the width-to-length (W/L) ratio of the driver transistor relative to that of the pass transistor. The ratio of the W/L values of the two transistors is known as the cell ratio and is commonly specified to be at least 3.0 or larger.
The physical adjustment of the W/L ratio for a metal-oxide-semiconductor (MOS) transistor requires a dimension change in either the width or the length of the gate electrode. In a VLSI circuit, where component sizes are typically reduced as much as possible, a constraint is placed on the maximum dimension of both the width and the length of the gate electrodes used in the circuit. This constraint limits the ability of a circuit designer to affect a parameter, such as an SRAM cell ratio. The cell designer is not free to arbitrarily select large values for one dimension relative to the other dimension in order to achieve the desired W/L ratio.
Recognizing a need to control the performance characteristics of one MOS transistor relative to that of another by means other than changing physical dimensions of the gate, technologists have developed other methods to control transistor performance characteristics. In one method, the control of the current gain of an pass transistor relative to a driver transistor is achieved by changing the doping concentration in the source-drain region. The gain of the pass transistor is reduced by omitting the N+ source region when forming the pass transistor. While this method is effective in changing current gain, the alteration can result in lower cell currents and slower read-access times. In another method, the thickness of the gate dielectric is increased in one transistor relative to the other. For example, the thickness of the gate dielectric layer is made large in the pass transistor relative to the gate dielectric thickness in the driver transistor. The pass transistor having the thicker dielectric layer has a lower current gain than the driver transistor. While changing the dielectric thickness is effective in altering current gain, additional high-precision processing steps are necessary to obtain an exact dielectric thickness differential between the two transistors.
Although the techniques described above overcome the limitations inherent in adjusting the dimensions of a gate electrode in a VLSI circuit, still more exact control of the current-gain parameter is needed to meet the demands of ever smaller circuit designs. Furthermore, the prior art methods for increasing memory cell stability involve retarding the performance of the pass transistor. In achieving a desired current gain differential, the method used should not result in abnormal transistor performance, such as degraded performance, and must be readily manufacturable.